The present invention generally relates to semiconductor devices, and in particular to a fabrication method of a semiconductor integrated circuit on a semiconductor substrate such that a first type device having a so-called semiconductor-on-insulator (SOI) structure wherein the device is provided on an insulator layer formed on the substrate, and a second type device or bulk semiconductor device wherein a substantial part thereof is formed within the substrate, are formed commonly on the same substrate.
Recently, there is a demand for high voltage integrated circuits used for display drivers. Such a high voltage integrated circuit is usually fabricated in the SOI structure in order to achieve a high breakdown voltage, as the conventional bulk structure devices, fabricated such that a substantial part thereof, such as the source and drain regions, are formed within the substrate by ion implantation and the like, are incapable of operating under high voltage environments unless a complicated isolation structure is formed within the substrate.
In particular, in the integrated circuits used for display drivers and the like, it is usual that the logic circuit part, to which no substantial high voltage is applied, is formed to have the bulk device structure using the well established fabrication process, and only the output part to which the high voltage is applied is formed on a field oxide region, in a form of the SOI structure.
FIG.1 shows a typical conventional integrated circuit wherein a first type semiconductor device having the SOI structure and a second type semiconductor device having the bulk structure, are provided on a common substrate 1.
Referring to FIG. 1, the substrate 1 is provided with a usual field oxide region 2 of silicon oxide for device isolation, and a high voltage MOSFET device 3 is provided on the field oxide region 2. Further, a logic device 4 which may be a CMOSFET device driven at a low voltage such as 5 volts, is provided on the substrate 1 in correspondence to the device region defined by the field oxide region 2.
FIGS. 2A-2E show the conventional process of fabricating the semiconductor device of FIG. 1.
Referring to the drawings, in a step of FIG. 2A, a thin silicon oxide film 11 is formed on the silicon substrate 1 by thermal oxidation for a thickness of about 500 .ANG.. Further, a silicon nitride (Si.sub.3 N.sub.4) film 12 is provided on the silicon oxide film 11 for a thickness of about 1000 .ANG. by a reduced pressure chemical vapor deposition (LPCVD) process. Further, the silicon oxide film 11 and the silicon nitride film 12 are patterned photolithographically to leave an oxidation resistant mask on the substrate 1 in correspondence to a device region 13 where a bulk semiconductor device such as the device 4 is to be formed. The silicon oxide film 11 under the silicon nitride film 12 acts as a buffer layer for relaxing the mechanical stress, which otherwise would be applied to the substrate 1 by the silicon nitride film 12 when the silicon oxide film 11 is omitted.
In a step of FIG. 2B, the substrate 1 thus obtained is subjected to a thermal oxidation process in a wet oxygen atmosphere at about 900.degree. C., whereby the field oxide region 2 is formed on the exposed part of the silicon substrate 1 for a thickness of about 1 um. This part of the process is well known as the LOCOS process.
In a step of FIG. 2C, the silicon nitride film 12 is removed by etching using a solution of phosphoric acid, and a polysilicon layer 5 is provided on the entire surface of the substrate 1 which is now covered by the field oxide region 2 as well as by the silicon oxide film 11, for a thickness of bout 0.5 .mu.m by the LPCVD process. Alternatively, a layer of non-crystalline silicon such as an amorphous silicon film may be used in place of the polysilicon layer 5.
In a step of FIG. 3D, the polysilicon layer 5 is irradiated by an energy beam such as a laser beam produced by a continuous oscillation of Ar-laser, and thereby the polysilicon layer 5 is crystallized to form a single crystal silicon layer 5'. In other words, a beam annealing process is performed in the step of FIG. 3D.
Next, in a step of FIG. 3E, the single crystal silicon layer 5' is removed by an isotropic dry etching process except for a device region 14 where an SOI device such as the device 3 is to be formed.
Further, in a step not illustrated, the bulk semiconductor device such as the device 4 and the SOI device such as the device 3 are provided respectively in correspondence to the device region 13 and the device region 14, and thereby a structure similar to the one described with reference to FIG. 1 is obtained. As already described, the SOI device 3 provided on the recrystallized single crystal silicon region 5' is insulated from the substrate 1 by the thick field oxide region 2, and can withstand a high voltage.
In such a conventional process of fabricating the semiconductor device, it is known that a problem arises in the step of beam annealing of FIG. 2D, such that a rupture occurs in the molten silicon layer 5' when the beam annealing condition, such as the beam energy, scanning speed and the like, is deviated even slightly from an optimum condition. FIG. 3 shows a typical example of the rupture occured in the re-crystallized silicon layer 5'. As will be seen from the drawing, there appears a thickened region in the layer 5' as a result of the rupture, and such a thickened region remains throughout various processes performed subsequently. Thereby, various undesirable effects are caused in the process and in the device characteristic.
Although the reason of this rupture, occurring at the time of beam annealing, is not fully explored, it is thought probable that the difference in the thermal conductivity between the device region 13 where the silicon layer 5' is contacted directly to the silicon substrate 1 and the device region 14 where the silicon layer 5' is separated from the substrate 1 by the field oxide region 2, causes a difference in the cooling rate at the time of crystallization of the molten silicon, and this difference in the rate of crystallization contributes to this rupture of the silicon layer 5' in some way.
On the other hand, it is known conventionally that silicon nitride shows an excellent wetting to molten silicon. Thus, there has been proposals, for example as disclosed in the Japanese Laid-open Patent Application No.58-14526, to provide an intervening silicon nitride layer between a silicon oxide layer and a silicon layer deposited thereon in a form of molten silicon layer to improve the process of forming a structure in which the silicon layer is provided on the silicon oxide layer. However, the foregoing process disclosed in the Japanese Laid-open Patent Application No. 58-14526 is not directed to the fabrication process of the semiconductor integrated circuits having both the bulk semiconductor devices and the SOI devices, and requires an extra step for providing the silicon nitride layer at the time of fabrication of the semiconductor device only for the purpose of improving the wetting, and the silicon nitride layer thus provided remains unnecessarily after the process of device fabrication is completed.